Scalable host controller for modular hardware accelerator

This paper presents a scalable host controller for modular hardware accelerator. Designing a hardware method of scalable host controller can handle multiple processing units at the same time. Currently in System on Chip (SoC) design, multiple processing units accessing the memory to request a task lead to inefficient communications due to bus congestion. In addition, designing a scalable host controller helps the transactions schedule consistently between different processing units in the modular hardware accelerator. In this paper, the hardware approach of scalable host controller design is expected to support up to seven different processing units.