DocumentCode
2731216
Title
Self-replicating process for micro interconnect array pattern using solder/polymer hybrid materials
Author
Yasuda, Kiyokazu
Author_Institution
Nagoya Univ., Nagoya, Japan
fYear
2010
fDate
1-4 June 2010
Firstpage
1416
Lastpage
1421
Abstract
In the modern packaging technologies highly condensed metal interconnects such as solder bumps, gold studs, or copper pillars are typically formed by high-cost processes. These methods inevitably require the precise controls of mutually dependant process parameters, which usually cause the difficulty of the change in the layout design for interconnects of chip to-chip, or chip-to-substrate. In order to overcome these problems, so far, the unique concept and methodology of self-assembly even in micro-meter scale were developed by the author. Self-replication for micro interconnect was firstly proposed, in which micro "twin droplets" out of continuous molten solder can form in a small parallel gap between two co-planar surfaces of chips and substrates with array copper traces (typically 100 to 300 μm pitches) using the vertical detaching movement in polymer resin. In this report the geometry and yielding ratio of vertical and lateral solder bump bridges before self-replication were compared with varying filler content, copper land pitch, and gap space. It was found that the formation of the vertically bridged bump arrays with 100 to 300 μm pitch can be achievable.
Keywords
Chip scale packaging; Conducting materials; Copper; Costs; Flip chip; Geometry; LAN interconnection; Polymers; Resins; Space technology;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
Conference_Location
Las Vegas, NV, USA
ISSN
0569-5503
Print_ISBN
978-1-4244-6410-4
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2010.5490814
Filename
5490814
Link To Document