Improving FPGA Design Robustness with Partial TMR

This paper describes an efficient approach of applying mitigation to an FPGA design to protect against single event upsets (SEUs). This approach applies mitigation selectively to FPGA circuit structures depending on their importance within the design. Higher priority is given to structures causing "persistent" errors within the design. For certain applications, applying selective mitigation to the persistent components can yield higher returns in reliability per unit cost than full mitigation. A software tool is also introduced which automatically classifies circuit structures based on this concept and applies triple modular redundancy (TMR) selectively based on the classification of the circuit structure