DocumentCode
2731412
Title
P-channel devices for half-micron CMOS: advantages of high-energy channel implantations
Author
Woerlee, P.H. ; Walker, A.J. ; Burgmans, A.L.J.
Author_Institution
Philips Res. Lab., Eindhoven, Netherlands
fYear
1989
fDate
17-19 May 1989
Firstpage
213
Lastpage
216
Abstract
The design and the characterization of p-channel devices for half-micron CMOS (complementary metal-oxide-semiconductor) with n+ -silicon gate material are described. Retrograde well technology is used in the fabrication for improved control of the short-channel effects. Excellent behavior has been observed for devices with effective channel length down to 0.4 μm. The properties of the buried channel devices are compared with those of the competing p+-gate surface channel devices. Hot carrier effects are discussed
Keywords
CMOS integrated circuits; VLSI; integrated circuit technology; 0.5 micron; buried channel devices; effective channel length; half-micron CMOS; high-energy channel implantations; hot carriers; n+-silicon gate material; p-channel devices; p+-gate surface channel devices; retrograde well technology; short-channel effects; CMOS technology; Degradation; Doping; Fabrication; Hot carriers; Implants; Laboratories; Leakage current; Lithography; MOS devices;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location
Taipei
Type
conf
DOI
10.1109/VTSA.1989.68616
Filename
68616
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