Impact of NBTI Induced Statistical Variation to SRAM Cell Stability

This work investigates the impact of negative bias temperature instability (NBTI) on the SRAM cell stability. As proposed by C. Wang et al., the stability of an SRAM cell can be determined by the peak current (I_CRIT) of the "N curve". In our experiments a typical NBTI stress was applied to one of the two pull up transistors part of an SRAM cell designed by using an advanced submicron CMOS technology. Both the mean and variance of the pMOSFET threshold voltage shift in saturation (DeltaVt_SAT) and the corresponding values of the I_CRIT shifts (DeltaI_CRIT) were measured. An experimental correlation between the means and the variances of both parameters shifts was established and found consistent with the predicted simulated values in the case of I_CRIT is degrading by only NBTI aging of the one or both pull up transistors. These results allow us to observe the direct impact of the NBTI shift of a pMOSFET transistor in a SRAM cell and the corresponding reduction to the static noise margin. In addition we propose, for the first time, a methodology to define a pMOSFET device NBTI target directly related to the SRAM cell stability and its dependence on SRAM design and the adopted CMOS technology. It is found that a more appropriate SRAM stability sensitive pMOSFET NBTI Vt _SAT target cannot be limited to the Vt_SAT mean shift, but needs as well a quantification of the allowed variance and initial SRAM I_CRIT distribution