CMOS image sensor binning circuit for low-light imaging

This work presents a column level binning circuit for a CMOS image sensor for detecting low-light imaging. A 2×2 kernel pixel binning (averaging) is employed in this design reducing the spatial resolution to 1/4 of the original size and every two columns of the pixel array share one binning circuit. The output signal of each pixel is sampled unto the binning circuit basically composed of two adjacent correlated double sampling circuits averaged by means of a row average switch. A 0.18um CMOS process was used to simulate the circuit and simulation results reveal a kernel averaging error of ≤2% for low-light conditions with a power consumption of 123.9uW.