Investigation for electromigration-induced hillock in a wafer level interconnect device

This paper investigates the electromigration induced hillock generation in a wafer level interconnect structure through a numerical approach. The driving force for electromigrationinduced failure includes the electron wind force, stress gradients, temperature gradients, as well as the atomic density gradient, which were neglected in many of the existing studies on electromigration. The parameter study for the Al line geometry with different width and thickness of a standard wafer level electromigration accelerated test (SWEAT) structure is investigated. The comparison of void/hillock formation and the time to failure (TTF) life through numerical example of the SWEAT structure with the measurement result is studied and discussed. Finally, the TTF life of a hillock is defined and discussed.