DocumentCode
2732505
Title
Design and fabrication of a reliability test chip for 3D-TSV
Author
Trigg, A.D. ; Yu, Li Hong ; Zhang, Xiaowu ; Chong, Chai Tai ; Kuo, Cheng Cheng ; Khan, Navas ; Daquan, Yu
Author_Institution
Inst. of Microelectron., A*STAR (Agency for Sci., Technol. & Res.), Singapore, Singapore
fYear
2010
fDate
1-4 June 2010
Firstpage
79
Lastpage
83
Abstract
A test chip has been designed and fabricated to validate the performance, yield and reliability of 3D chipstacks using Through Silicon Vias (TSVs). The test chip contains test structures designed to measure the electromigration performance of TSVs and microbump, thermal performance, stress in the chip as a result of thinning and die stacking, and corrosion related to moisture ingress. The structures are designed to facilitate failure analysis, allowing fault isolation to be done by electrical characterization as far as possible.
Keywords
Corrosion; Electromigration; Fabrication; Moisture measurement; Semiconductor device measurement; Silicon; Stacking; Stress measurement; Testing; Thermal stresses;
fLanguage
English
Publisher
ieee
Conference_Titel
Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
Conference_Location
Las Vegas, NV, USA
ISSN
0569-5503
Print_ISBN
978-1-4244-6410-4
Electronic_ISBN
0569-5503
Type
conf
DOI
10.1109/ECTC.2010.5490889
Filename
5490889
Link To Document