• DocumentCode
    2733304
  • Title

    Image Border Management for FPGA Based Filters

  • Author

    Bailey, Donald G.

  • Author_Institution
    Sch. of Eng. & Adv. Technol., Massey Univ., Palmerston North, New Zealand
  • fYear
    2011
  • fDate
    17-19 Jan. 2011
  • Firstpage
    144
  • Lastpage
    149
  • Abstract
    Most of the literature on image filtering using FPGAs focuses on the normal case when the window is completely within the image. The exception - when the window is partly off the edge of the image - is rarely considered. If not managed appropriately, handling these exceptions can take up more resources than the main operation. Efficient techniques are presented that manage the image borders by reusing the logic for the standard case. A technique is described for overlapping the priming and flushing phases at the end of row and end of frame that reduce the overhead in time critical applications.
  • Keywords
    field programmable gate arrays; filters; image processing; FPGA; filters; flushing phases; image borders; image filtering; time critical applications; Clocks; Delay; Field programmable gate arrays; Image edge detection; Pixel; Registers; Streaming media; image processing; pipeline; window filters;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on
  • Conference_Location
    Queenstown
  • Print_ISBN
    978-1-4244-9357-9
  • Electronic_ISBN
    978-0-7695-4306-2
  • Type

    conf

  • DOI
    10.1109/DELTA.2011.34
  • Filename
    5729556