Mitigating heat dissipation and thermo-mechanical stress challenges in 3-D IC using thermal through silicon via (TTSV)

Thermal modeling of a 3-D IC stack consists of three IC layers bonded back-to-face (or face up) is performed. Significant temperature rise in the top layers is projected with the presence of dielectric isolation films between the IC layers. It is found that by inserting electrically isolated thermal through silicon via (TTSV) having Cu core and oxide liner that extends across the layers to the silicon substrate, significant temperature reduction can be achieved in the maximum temperature. The temperature profile of the 3-D IC stack depends strongly on materials selection for TTSV liner and conductor core, as well as TTSV dimensions. Thermo-mechanical stress induced by TTSV is also discussed and several approaches are proposed to control this stress. Simulation data also suggest that TTSV is useful in mitigating heat dissipation challenges in face-to-face bonding orientation and logic-on-memory stacking.