Design of a 3.3 V 12 bit CMOS D/A converter with a high linearity

Author

Ryu, Ki-Hong ; Yoon, Kwang Sub ; Min, Hong Ki

Author_Institution

Dept. of Electron. Eng., Inchon Univ., South Korea

fYear

1998

fDate

9-12 Aug 1998

Firstpage

538

Lastpage

541

Abstract

This paper describes a 3.3 V, 65 MHz 12 bit CMOS current-mode DAC designed with a 8 MSB current matrix stage and a 4 LSB binary weighting stage. The linearity errors caused by a voltage drop of the ground line and a threshold voltage mismatch of transistors have been reduced by the symmetrical routing method with a ground line and the tree structure bias circuit, respectively. In order to realize a low glitch energy, a cascode current switch has been employed. The simulation results of the designed DAC show a conversion rate of 65 MHz, a power dissipation of 71.7 mW, a DNL of ±0.2 LSB and an INL of ±0.8 LSB with a single power supply of 3.3 V for a 0.6 μm n-well CMOS technology

Keywords

CMOS integrated circuits; current-mode circuits; digital-analogue conversion; errors; integrated circuit design; network routing; 0.6 micron; 12 bit; 3.3 V; 65 MHz; 71.7 mW; CMOS D/A converter; CMOS current-mode DAC; binary weighting stage; cascode current switch; current matrix stage; ground line; high linearity; linearity errors reduction; low glitch energy; n-well CMOS technology; symmetrical routing method; tree structure bias circuit; CMOS technology; Circuit simulation; Linearity; Matrix converters; Power dissipation; Routing; Switches; Symmetric matrices; Threshold voltage; Tree data structures;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-8914-5

Type

conf

DOI

10.1109/MWSCAS.1998.759549

Filename

759549