Acceleration of Functional Validation Using GPGPU

Author

Suresh, Lalith ; Rameshan, Navaneeth ; Gaur, M.S. ; Zwolinski, Mark ; Laxmi, Vijay

Author_Institution

Malaviya Nat. Inst. of Technol., Jaipur, India

fYear

2011

fDate

17-19 Jan. 2011

Firstpage

211

Lastpage

216

Abstract

Logic simulation of a VLSI chip is a computationally intensive process. There exists an urgent need to map functional validation algorithms onto parallel architectures to aid hardware designers in meeting time-to-market constraints. In this paper, we propose three novel methods for logic simulation of combinational circuits on GPGPUs. Initial experiments run on two methods using benchmark circuits using NVIDIA GPGPUs suggest that these methods can be used for accelerating the EDA design flow process.

Keywords

VLSI; benchmark testing; combinational circuits; computer graphic equipment; coprocessors; electronic design automation; integrated logic circuits; logic simulation; parallel architectures; time to market; EDA design flow process; GPGPU; VLSI chip; benchmark circuit; combinational circuit; electronic design automation; functional validation; general purpose graphics processing units; logic simulation; parallel architecture; time-to-market; Computational modeling; Graphics processing unit; Instruction sets; Integrated circuit modeling; Kernel; Logic gates; Pipeline processing; EDA; GPGPU; Logic Simulation;

fLanguage

English

Publisher

ieee

Conference_Titel

Electronic Design, Test and Application (DELTA), 2011 Sixth IEEE International Symposium on

Conference_Location

Queenstown

Print_ISBN

978-1-4244-9357-9

Type

conf

DOI

10.1109/DELTA.2011.46

Filename

5729569