Implementation of programmable digital sigmoid function circuit for neuro-computing

Author

Al-Nsour, Mahmoud ; Abdel-Aty-Zohdy, Hoda S.

Author_Institution

Microelectron. Syst. Design Lab., Oakland Univ., Rochester, MI, USA

fYear

1998

fDate

9-12 Aug 1998

Firstpage

571

Lastpage

574

Abstract

A programmable digital sigmoid function generator circuit has been designed and implemented. The circuit is based on second order approximation of the nonlinear sigmoid function and utilizing its characteristics. It offers an easy way of changing the steepness of the function in the transition state. In addition, the squaring function operation was implemented using combinational logic. This offers a compact realization of the system as a parallel bit architecture. The maximum output error is .047 and the average error is within 0.01. Simulations show that the circuit operates satisfactorily up to 50 MHz. The digital VLSI circuit has been fabricated using MOSIS/AMI N-well 1.2 μm CMOS double metal process. It occupies an area of 900×450 μm²

Keywords

CMOS digital integrated circuits; VLSI; neural chips; parallel architectures; programmable circuits; 0 to 50 MHz; 1.2 micron; MOSIS/AMI N-well CMOS double metal process; combinational logic; digital VLSI; neuro-computing; output error; parallel bit architecture; programmable digital sigmoid function circuit; second order approximation; squaring function operation; transition state; Artificial neural networks; Circuit synthesis; Design engineering; Laboratories; Microelectronics; Neural networks; Neurons; Piecewise linear approximation; Silicon; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1998. Proceedings. 1998 Midwest Symposium on

Conference_Location

Notre Dame, IN

Print_ISBN

0-8186-8914-5

Type

conf

DOI

10.1109/MWSCAS.1998.759557

Filename

759557