• DocumentCode
    2733566
  • Title

    Challenges of Cu wire bonding on low-k/Cu wafers with BOA structures

  • Author

    Chu-Chung Lee ; Higgins, Leo M

  • Author_Institution
    Freescale Semicond., Inc., Austin, TX, USA
  • fYear
    2010
  • fDate
    1-4 June 2010
  • Firstpage
    342
  • Lastpage
    349
  • Abstract
    This study describes the development of a Cu wire bond assembly solution for ICs using low dielectric constant (low K) dielectrics and Cu interconnect, with bond pads designed with aggressive BOA (Bond Over Active) design rules. The various wire bonding challenges imposed by the bond pad material stack and the aggressive high density BOA design will be discussed. It is desired to use the aggressive BOA rules since this provides greater design flexibility and can result in a smaller die size. The suitability of two different bond pad and BOA structures, currently used with Au wire bonding, was evaluated to assess viability for high reliability Cu wire bonding. The assembly process, the bond quality requirements, the reliability stress testing, and the impact on the Cu wire bonds will be described. Corrosion of the Cu-Al IMC (interface metallic compound) bond phase(s) that can be seen with environmental stress testing will be discussed. The hypothesis that the IMC corrosion is due to attack by impurities in the epoxy-based molding compound will be discussed. The results of a thermal aging study (150°C / 504 hrs), demonstrating the slow growth of the CuAl IMC structure, and analysis of the Cu-Al IMC phases will also be reported.
  • Keywords
    ageing; aluminium alloys; copper alloys; integrated circuit interconnections; lead bonding; low-k dielectric thin films; moulding; reliability; Au wire bonding; BOA structure design; Cu interconnect; Cu wire bond assembly process; Cu-Al; IC; bond over active design rules; bond pad material stack; bond phase; environmental stress testing; epoxy-based molding compound; interface metallic compound; low dielectric constant; low-k-Cu wafers; reliability stress testing; thermal aging; Assembly; Corrosion; Dielectric constant; Dielectric materials; Gold; Impurities; Testing; Thermal stresses; Wafer bonding; Wire;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electronic Components and Technology Conference (ECTC), 2010 Proceedings 60th
  • Conference_Location
    Las Vegas, NV
  • ISSN
    0569-5503
  • Print_ISBN
    978-1-4244-6410-4
  • Electronic_ISBN
    0569-5503
  • Type

    conf

  • DOI
    10.1109/ECTC.2010.5490949
  • Filename
    5490949