Test Generation Approach for Post-Silicon Validation of High End Microprocessor

Post-Silicon Validation faces numerous challenges in the areas of test generation efficiency, time utilization and comprehensive coverage of the various functionalities of advanced microprocessors. The proposed approach uses the concept of building a Master Test Program that is used to build multiple test-streams by utilizing an instruction pool and a data pool. It utilizes lightweight modules such as the Instruction Classifier and Organizer and the Data Pool Generator that generate test streams on the fly. A key advantage of this is that it extends coverage of the processor state space while reducing the build time greatly.