• DocumentCode
    2733636
  • Title

    Degradation Mechanism in Low-Temperature P-Channel Polycrystalline Silicon TFTs Under Dynamic Stress

  • Author

    Toyota, Y. ; Matsumura, M. ; Hatano, M. ; Shiba, T. ; Ohkura, M.

  • Author_Institution
    Central Res. Lab., Hitachi Ltd., Tokyo
  • fYear
    2006
  • fDate
    26-30 March 2006
  • Firstpage
    729
  • Lastpage
    730
  • Abstract
    Pronounced device degradation and temperature dependence of p-channel polycrystalline silicon thin-film transistors (polysilicon TFTs) under dynamic stress were investigated. This device degradation is due to the trap states produced by repetition between electron injection and hole injection. The degradation is strongly dependent on the number of trapped holes and the location of the hole-injection region. The analysis of activation energy affirms that the rapid degradation at high temperature is caused by an increase in the number of trapped holes, to which the negative-bias-temperature stress significantly contributes
  • Keywords
    electron traps; hole traps; semiconductor device reliability; silicon; stress effects; thin film transistors; Si; device degradation; dynamic stress; electron injection; hole injection; hole-injection region; negative-bias-temperature; p-channel polycrystalline silicon TFT; temperature dependence; thin-film transistors; trap states; trapped holes; Charge carrier processes; Degradation; Displays; Electron traps; Laboratories; Silicon; Spontaneous emission; Stress; Temperature dependence; Thin film transistors;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Reliability Physics Symposium Proceedings, 2006. 44th Annual., IEEE International
  • Conference_Location
    San Jose, CA
  • Print_ISBN
    0-7803-9498-4
  • Electronic_ISBN
    0-7803-9499-2
  • Type

    conf

  • DOI
    10.1109/RELPHY.2006.251346
  • Filename
    4017287