Advanced approach for surface decoupling in crystalline silicon solar cells

Texturing and polishing crystalline silicon in the PV industry are both time consuming and inefficient, the need for a streamlined solution is prevalent. To obtain high conversion efficiency surface decoupling is needed, one side of the wafer is ideally textured while the other is completely polished. The front is textured to collect the maximum number of photons while the rear acts as a perfect mirror to reflect all outgoing light back into the silicon for absorption. In industry, crystalline silicon wafers initially undergo a saw damage etch (SDR) in which 10μm of silicon is removed from each side. Wafers are then placed in an alkaline texturing solution which textures both sides which removes another 5μm from each side. Finally the wafers are single side polished, removing a final 10μm from one side. This industrial process results in a total silicon loss of 40μm and a complete surface decoupling cycle time in the order of an hour from as cut until diffusion ready. For an industrial wafer thickness of 180μm more than 20% of the silicon is lost. In addition to silicon loss, the multiple wet processing steps needed for decoupling are time consuming and hinder high throughput manufacturing needed to achieve the ultimate goal of a low per watt peak price. To increase efficiency more process steps are needed, cell concepts such as the i-PERC, i-PERL and the i²-BC all need an increasing number of process steps leading to higher efficiencies. As the number of process steps and complexity increases, the variability in the overall process will increase as well; this will ultimately make these concepts unrealizable by industry. It is desirable to develop processes and techniques that are of multi-purpose. Such a technique is proposed in this paper, this technique decouples the front and rear surfaces and utilizes only one wet process step for both the texturing and polishing. This process simplification leads to savings by- - decreasing costly cycle time, saving consumables and reducing the amount of silicon loss. The complete process takes a few minutes from an as cut wafer to a fully decoupled wafer, ready for further processing. Thus far, a top efficiency of 18.4% has been achieved (37.3 mA/cm², 640 mV, FF 77.0 %) on full 156cm² wafers with screen printed contacts and local Al-BSF, an encouraging proof of concept.