Adaptive hysteretic comparator with opamp threshold level setting

This paper presents the design of an adaptive hysteretic comparator optimized for noisy environment. It features an input rail-to-rail opamp which uses feedback networks to set varying hysteretic thresholds while maintaining a constant hysteretic band for increased noise immunity and stability. The chip which can resolve up to 9 bits consumes a total power of 3.8 mW and takes an active area of 0.021 mm² in a 2P3M 0.5 mum CMOS process with 20 ns propagation delay.