DocumentCode
2733784
Title
Balanced multi-level multi-way partitioning of large analog circuits for hierarchical symbolic analysis
Author
Tan, Xiang-Dong ; Shi, C. J Richard
Author_Institution
Dept. of Electr. Eng., Washington Univ., Seattle, WA, USA
fYear
1999
fDate
18-21 Jan 1999
Firstpage
1
Abstract
Symbolic analysis of analog circuits is important in analog design automation. However, it is limited to the analysis of small analog circuits where exact symbolic expressions are required. In this paper, we present an efficient algorithm for partitioning large general analog circuits into smaller subcircuits so that symbolic analysis can be performed hierarchically. Experimental results have demonstrated that our method outperforms the best partitioning-based symbolic analyzer SCAPP
Keywords
analogue integrated circuits; circuit CAD; circuit analysis computing; symbol manipulation; analog design automation; balanced multi-level multi-way partitioning; hierarchical symbolic analysis; large analog circuits; Admittance; Algorithm design and analysis; Analog circuits; Design automation; Equations; Integrated circuit manufacture; Partitioning algorithms; Performance analysis; Semiconductor device manufacture; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location
Wanchai
Print_ISBN
0-7803-5012-X
Type
conf
DOI
10.1109/ASPDAC.1999.759572
Filename
759572
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