DocumentCode :
2734212
Title :
Sub-100 micron pitch stencil printing for wafer scale bumping
Author :
Desmulliez, M.P.Y. ; Kay, R.W. ; Abraham, E. ; de Gourcuff, E. ; Jackson, G.J. ; Steen, H.A.H. ; Liu, C. ; Conway, P.P.
Author_Institution :
MicroStencil Ltd., Livingston
fYear :
2005
fDate :
27-29 June 2005
Firstpage :
1
Lastpage :
7
Abstract :
This paper presents recent work on solder paste printing for wafer-level bumping at sub 100mum pitch using Pb-free solder paste with IPC type-6 (15-5mum) particle size distributions. Consistent sized paste deposits have been produced onto wafers at such a pitch using stencil printing. Furthermore, a stencil printing evaluation has determined the impact that the print parameters have on the reproducibility of the deposits. With the reduction of pitch and aperture size, large volumes of paste are required during reflowing of the fine particle solder paste to allow sufficient stand-off between the flip chip device and substrate. This volume of pastes affects also the print consistency and uniformity of the bumps generated. Printing defects from a large number of printing trials have been examined statistically for several bump geometries. The best print parameters were then used to print paste deposits onto wafers containing bond pads for reflow. Stencil printing process at ultra fine pitch demands refinements to both solder paste design and stencil manufacturing technology. Advancements in stencil fabrication methods have produced ´state-of-the-art´ stencils exhibiting highly defined shaped apertures with smooth walls at ultra fine pitch, thus allowing for improved solder paste release at very small pitch and aperture size dimensions. The engineering of the paste rheology in terms of shear thinning, tackiness and visco-elastic properties was carried out by varying the metal content and flux type. The design of new paste material has also be conducted alongside a design of experiments to adjust printing parameters such as printing speed, pressure, print gap and separation speed to allow for a practical process window
Keywords :
fine-pitch technology; flip-chip devices; solders; wafer level packaging; 15 to 5 micron; design of experiments; flip chip device; lead free solder paste; paste rheology; printing defects; shear thinning; solder paste design manufacturing technology; solder paste printing; stencil manufacturing technology; stencil printing process; substrate; tackiness property; visco-elastic property; wafer scale bumping; Apertures; Fabrication; Flip chip; Geometry; Manufacturing processes; Printing; Refining; Reproducibility of results; Rheology; Wafer bonding;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Density Microsystem Design and Packaging and Component Failure Analysis, 2005 Conference on
Conference_Location :
Shanghai
Print_ISBN :
0-7803-9292-2
Electronic_ISBN :
0-7803-9293-0
Type :
conf
DOI :
10.1109/HDP.2005.251378
Filename :
4017419
Link To Document :
بازگشت