NOR/OR register based ECL circuits for maximum data rate

We present a simple efficient general approach of increasing the clock rate of ECL circuits. The key ECL feature used here is the fact that a single transistor added to a register circuit provides a logic NOR function at very small additional delay (0.7 ps in a 200 GHz SiGe BiCMOS technology). Composing the logic functions entirely of such NOR/OR elements merged into registers increases the clock rate substantially. For a XOR function, the predicted gain in speed is 38% over the current state of the art, and 60% over a single gate. Two pseudo-random generator test chips verify the prediction.