High Strain Rate Testing of Solder Interconnections

Understanding the response of the board-to-package (2nd level) interconnections to loading at high strain rates is essential for the design against drop impact failure. To obtain such properties, the impact tester used must provide results for energy to failure and information on impact force and displacement. Knowledge of impact force is essential for quantifying the strength of the interconnection and allows quantitative design against failure. It also allows one-to-one comparison with the failure force measured in a standard quasi-static shear test. This paper reports on a newly-developed micro-impact tester that is capable of registering the dynamic impact force and displacement during the high-strain rate loading of an interconnection. The micro-impact tester was used to evaluate the high strain-rate characteristics of various types of solder interconnections. The interconnections were varied with respect to the type of leaded and lead-free solder alloys, thermal histories, pad finishes and pad definitions. The following observations have been made with regard to the peak loads and failure modes obtained in both static shear tests and high strain rate impact tests: 1) Peak loads obtained from impact tests are between 30% to 100% higher than that obtained from static shear tests for all combinations of solder alloy and pad finish; 2) The SnPb solder alloy had the maximum energy to failure for all pad finishes. Of all the lead-free solders, the SnAg solder alloy had the highest energy to failure; 3) Static shearing induces only bulk solder failure for all combinations of solder alloy and pad finish. Impact testing tends to induce bulk solder failure for SnPb solder and a mixture of bulk and intermetallic failure in all the lead-free solder alloys for all pad finishes; and 4) In general, the peak loads obtained for NSMD pads are significantly lower than that for SMD pads. The results obtained so far have highlighted the vulnerability of NSMD pads to drop impact. T- - his is especially important as I/O pitch is ever decreasing, which will inevitably force pad design to become NSMD due to the more lenient design rules. In addition, the risk of cratering failure will be likely to increase with decreasing pad size