A mixed-signal adder based on the Continuous Valued Number System

Continuous Valued Number System (CVNS) representation enables us to integrate complex analog processing functions within digital signal processing units. The CVNS representation is more compatible with analog signals and system, however, it can be applies to applications where traditionally digital arithmetic has been used. The resulted systems usually have compact designs, with reduced number of interconnections, and higher speed of operation. In this paper, design of a mixed signal CVNS adder is proposed, which is used for two operand binary addition. The overall speed of the CVNS adder depends on the analog modular reduction circuits. This paper addresses the limitations in the speed of CVNS adders, and proposes a new method for eliminating this operation from the adder.