DocumentCode
2734711
Title
The extended partitioning problem: hardware/software mapping and implementation-bin selection
Author
Kalavade, Asawaree ; Lee, Edward A.
Author_Institution
Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA
fYear
1995
fDate
7-9 Jun 1995
Firstpage
12
Lastpage
18
Abstract
The extended partitioning problem is the joint problem of mapping nodes in a precedence graph to hardware or software, and within each mapping, selecting an appropriate implementation for each node. The end-goal is to minimize the hardware area, subject to architectural and performance constraints. This is an NP-complete problem; we present an efficient heuristic called MIBS to solve it. The MIBS (Mapping and Implementation-Bin Selection) algorithm solves the extended partitioning problem by decomposing it into an iterative process consisting of two steps: mapping and implementation-bin selection (IBS). The GCLP (Global Criticality/Local Phase-driven) algorithm computes a mapping by using an adaptive optimization objective at each iteration. This objective is selected on the basis of a global time criticality measure and local optimality measures. The IBS algorithm solves the implementation-bin selection problem. It uses a bin sensitivity measure which correlates the implementation bin motion with the overall hardware area reduction, to determine the implementation bin of a node for a given mapping. Experimental results indicate that the added dimension of design flexibility (offered by implementation bins) can be used effectively in partitioning to reduce the overall area. The MIBS algorithm has O(|N| 3) complexity, with a solution quality comparable to that of ILP (integer linear programming)
Keywords
computational complexity; directed graphs; iterative methods; logic CAD; logic partitioning; minimisation; resource allocation; software engineering; GCLP algorithm; MIBS heuristic algorithm; NP-complete problem; adaptive optimization objective; architectural constraints; bin sensitivity measure; complexity; design flexibility; extended partitioning problem; global criticality; global time criticality measure; hardware area reduction; hardware/software mapping; implementation bin motion; implementation-bin selection; iterative process; local optimality measures; local phase-driven algorithm; node implementation selection; performance constraints; precedence graph node mapping; solution quality; Area measurement; Design optimization; Hardware; Iterative algorithms; Motion measurement; NP-complete problem; Partitioning algorithms; Software algorithms; Software quality; Time measurement;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 1995. Proceedings., Sixth IEEE International Workshop on
Conference_Location
Chapel Hill, NC
ISSN
1074-6005
Print_ISBN
0-8186-7100-9
Type
conf
DOI
10.1109/IWRSP.1995.518565
Filename
518565
Link To Document