Optimizing BIST and repair logic for embedded memories

This paper describes certain practical issues on designing and implementing built-in self-test circuits for testing and repairing a group of embedded memories of different types and sizes. Various test architectures presented in this paper provide for different optimizing criteria such as test time, routing feasibility, silicon overhead, and dynamic power compliance. The repair circuits are based on the most popular and widely accepted built-in-self-test strategy, and are power aware, repair friendly, and supports scan based testing of random glue logic in SOC designs. These features are useful primarily in SOC testing because such designs typically contain many memories that are large and repairable. Without an effective repair scheme, the production yield of a SOC containing a large numbers of embedded memory types and instances may severely be compromised.