DocumentCode
2734726
Title
Enhancing parallel-prefix structures using carry-save notation
Author
Chen, Jun ; Stine, James E.
Author_Institution
Dept. Electr. & Comput. Eng., Oklahoma State Univ., Stillwater, OK
fYear
2008
fDate
10-13 Aug. 2008
Firstpage
354
Lastpage
357
Abstract
Parallel prefix adders draw much attention because of their logarithmic delay. This paper proposes a scheme to enhance parallel prefix adders by incorporating the idea of carry-save addition within the prefix tree. Results are given for several designs using a publicly available nanometer library.
Keywords
VLSI; adders; carry logic; logic design; nanoelectronics; trees (mathematics); VLSI architectures; carry-save notation; logarithmic delay; parallel prefix adders designs; parallel-prefix structures enhancement; publicly available nanometer library; size 90 nm; Added delay; Computer architecture; Concurrent computing; Design engineering; Equations; Libraries; Logic design; Signal generators; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location
Knoxville, TN
ISSN
1548-3746
Print_ISBN
978-1-4244-2166-4
Electronic_ISBN
1548-3746
Type
conf
DOI
10.1109/MWSCAS.2008.4616809
Filename
4616809
Link To Document