Increased energy efficiency and reliability of ultra-low power arithmetic

To achieve ultra-low energy datapath units, probabilistic computing can be employed such that supply voltages are lowered to near threshold or subthreshold levels causing probabilistic operation of devices. The limit to voltage scaling for deterministic computing is the thermodynamic limit where gates begin to fail on a probabilistic basis due to thermal noise. It has been shown in prior work that probabilistic datapath units can be designed to compute successfully and that this operation is desireable given the extreme energy savings available. Continuing with this work, 2 novel theorems are developed proving which gates and circuit topologies are most amenable to probabilistic errors. To illustrate these theorems at work, a case study of a full adder is given that shows the most energy efficient full adder design for a given error rate under ultra-low supply voltage conditions where the thermal noise constraint exists. Simulation results using TSMC 0.25 mum technology are given verifying the ultra-low power, probabilistic full adder designs. It will be shown that for a given error rate, the energy consumption of a full adder can be improved up to 6X over the baseline case that optimizes for speed using these probabilistic design principles. Further, over 10X energy savings is acheived for a full adder over the deterministic case.