A pFET-access radiation-hardened SRAM for extreme environments

This paper presents the design of a 128 times 12 SRAM block with each SRAM unit containing 2 pFET access transistors and a precharge-to-ground system for the purpose of minimizing its layout feature size. By using these techniques, the feature size of the SRAM cell with guard rings was effectively reduced to 12.6 mum times 17.9 mum, incorporating IBM SiGe5AM 0.5 mum process in order to make the SRAM suitable for extremely low temperature environment. To improve the reliability, several radiation hardening techniques have also been applied: guard rings were designed to separate pFET and nFET regions of the SRAM cell to prevent potential latch-up, and an error-correcting code (ECC) was also included to correct soft errors caused by ionizing radiation. Cryogenic testing has been performed to verify the SRAM is able to operate correctly over a temperature range of 2 K to 297 K.