DocumentCode
2735052
Title
A case study of system synthesis with non-synthesizable components using extended VHDL
Author
Babcock, J. D Sterling ; Dollas, Apostolos
Author_Institution
Dept. of Electr. Eng., Duke Univ., Durham, NC, USA
fYear
1995
fDate
7-9 Jun 1995
Firstpage
168
Lastpage
173
Abstract
Extensions to VHDL have been defined in order to produce a compiler that allows for system design with synthesizable and non-synthesizable multi-chip subsystems. The compiler has been completed and this paper presents a case study that has been made to evaluate the merits and limitations of this approach. Finally, a brief discussion is made of the error generation. Capability that results from the use of formal methods in the definition of the VHDL language extensions
Keywords
hardware description languages; logic CAD; logic design; compiler; error generation; extended VHDL; formal methods; multi-chip subsystems; nonsynthesizable components; system synthesis; Computer aided software engineering; Design automation; Design engineering; Design methodology; Hardware; Libraries; Production; System-level design; Testing;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 1995. Proceedings., Sixth IEEE International Workshop on
Conference_Location
Chapel Hill, NC
ISSN
1074-6005
Print_ISBN
0-8186-7100-9
Type
conf
DOI
10.1109/IWRSP.1995.518587
Filename
518587
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