Efficient power modeling for on-chip global interconnects

The demand for powerful computational machines using scaled technologies has brought power dissipation to the forefront. Hence there is a need to accurate model power dissipation in high speed VLSI chips. The power consumption of interconnects has become an important issue as technology scales down. Therefore efficient power modeling of interconnects are necessary where inductance effect is dominant. The width of an interconnect line affects the total power consumed by a circuit. A trade off exists between the dynamic power and the short-circuit power dissipated in inductive interconnect. The optimum line width that minimizes the total transient power dissipation is discussed in this paper. Considering the driver size in the design process, the optimum wire and driver size that minimizes the total transient power is also determined. Closed form solutions are presented for inserting repeaters into RLC lines that are highly accurate with respect to numerical solutions. Considering inductance in repeater insertion significantly saves the repeater area and power consumption. Thus, the importance of inductance in high performance VLSI design methodologies will increase as technologies scale.