DocumentCode
2735210
Title
A 145 MHz user-programmable gate array
Author
Simões, Eduardo Do Valle ; Barone, Dante Augusto Couto
Author_Institution
Federal Univ. of Rio Grande do Sul, Porto Algere, Brazil
fYear
1995
fDate
7-9 Jun 1995
Firstpage
226
Lastpage
232
Abstract
This work aims to present the most relevant results derived from the development of a novel FPGA matrix. Nevertheless its capacity, its highlights are low cost and its ability to deal with high frequencies. This prototype matrix, named FLECHA, presents some structural novelties, as a different approach to perform the interconnections between logic cells and I/O pads and an internal controller. One of the major contributions of this work deals with the strategy of placing the logic cells in rows, allowing a drastic reduction of the number of switches without reducing interconnection capacity between logic cells and I/O pads. Following this principle, a new matrix presenting 600 equivalent gates was constructed including 40 logic cells and 40 programmable I/O pads. The FLECHA matrix is intended to implement simple logic functions as for fast “glue logic” between processors and memories, reaching an operational frequency of l45 MHz
Keywords
circuit analysis computing; field programmable gate arrays; logic design; programmable logic arrays; 145 MHz; I/O pads; glue logic; interconnection capacity; internal controller; logic cells; prototype matrix; simple logic functions; structural novelties; user-programmable gate array; Costs; Field programmable gate arrays; Frequency; Logic arrays; Logic devices; Logic functions; Programmable logic arrays; Prototypes; Signal processing; Switches;
fLanguage
English
Publisher
ieee
Conference_Titel
Rapid System Prototyping, 1995. Proceedings., Sixth IEEE International Workshop on
Conference_Location
Chapel Hill, NC
ISSN
1074-6005
Print_ISBN
0-8186-7100-9
Type
conf
DOI
10.1109/IWRSP.1995.518596
Filename
518596
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