New RF LDMOS structure with improved power added efficiency for 2 GHz power amplifiers

For 2 GHz cellular applications, it is important to raise the power-added efficiency of the RF power amplifier. A lower output capacitance of the transistor is a vital factor to obtain such a higher efficiency. In order to improve the LDMOS output properties, a new partial SOI structure is proposed in this paper. For the new structure, we achieved a 57% reduction of the output capacitance and a 37% output power increase. Also, the oxide layer under the drain can divert some electric field, therefore for the devices with the same blocking voltage capability, the proposed design needs a thinner epi layer. This decrease is in the thickness of P⁺ sinker region as well as the dimension of the device. These properties prove to be of great advantage in power amplification applications, as they would maximize power added efficiency (PAE) and integration ability. Laboratory measurement results were obtained to verify the proposed concept