Test calculation for logic and short-circuit faults in digital circuits

In the first part, the paper presents a test calculation principle which serves for producing tests of logic faults in digital circuits. The name of the principle is composite justification. The considered fault model includes stuck-at-0/1 logic faults. Both single and multiple faults are included. In this paper only combinational logic is taken into consideration. The computations are performed at the gate level. In the second part of the paper, the composite justification is extended to an other fault class, namely, short-circuit faults. A short circuit is an erroneous galvanic coupling between two circuit lines. The calculation principle is comparatively simple. It is based only on successive line-value justification, and it yields an opportunity to be realized by an efficient computer program.