Low power register allocation algorithm using graph coloring

Proposes a low power register allocation algorithm using graph coloring for minimal register for high level synthesis. The proposed algorithm constructs an interference graph consisting of the intermediate representation CFG to the VHDL description. The interference graph for the minimal selected color selects a positional node on the stack. Next, the inserted spill code and the graph coloring process executes for optimal register allocation. Hence, the registers are optimally reduced so that the power consumption is reduced. The proposed algorithm has been shown to have this result compared with other allocation techniques through benchmark experiments