Title :
Generalized wiring rules for CMOS circuits
Author :
Tomczak, James J.
Author_Institution :
IBM Gen. Technol., Essex Junction, VT, USA
Abstract :
A description is given of the impact of card wiring nets on signals generated by CMOS chips. Card nets driven by CMOS circuits are treated as transmission lines with lumped capacitances attached at points along the line, representing connections to other CMOS chips. Evaluation of overvoltage and undervoltage conditions, available noise margin, and reflection settling time is discussed. Allowable net length, effect of waveform rise and fall time, and of receiver loading on delays for typical net types is described
Keywords :
CMOS integrated circuits; delay lines; logic design; printed circuits; transmission line theory; CMOS circuits; card wiring nets; delays; lumped capacitances; net length; noise margin; overvoltage conditions; receiver loading; reflection settling time; rise time effects; signal degradation; transmission lines; undervoltage conditions; wiring rules; Acoustic reflection; CMOS technology; Delay effects; Delay lines; Driver circuits; Equations; Impedance; Signal generators; Voltage; Wiring;
Conference_Titel :
Custom Integrated Circuits Conference, 1988., Proceedings of the IEEE 1988
Conference_Location :
Rochester, NY
DOI :
10.1109/CICC.1988.20921
