A digital pseudo background correction method in pipelined ADCs

This paper presents a pseudo-background calibration method for the pipelined ADCs in which a main ADC and an extra low resolution, low speed ADC are used. The proposed method uses foreground calibration scheme for the main ADC, but at the same time, it works without any interruption in the normal conversion process by using of the extra ADC for the conversion of the skipped samples. The error associated with the extra ADC, its impact on the overall behavior of the ADC, and its distribution behavior are theoretically analyzed, and the results are verified by simulation. A 12-bit 1.5 bit/stage pipelined ADC and a 12-bit 1.5 bit/stage cyclic ADC are used for the main and the extra ADCs respectively.