12.4% efficient freestanding 30µm ultra-thin silicon solar cell using a-Si/c-Si heterostructure

The goal of this work is to demonstrate and analyze heterojunction devices on ultra-thin silicon wafers with imperfect surfaces and lower minority carrier lifetimes. Our previous results show intrinsic amorphous-Si passivation (i-a-Si) gives surface recombination velocity, S ~ 20 cm/sec on freestanding 35 μm Si wafers (Chhabra et al., 2008), and the work presented in this paper shows S ~ 84 cm/sec on chemically etched wafers. The degradation in the S values is assumed mainly due to the contamination in the PECVD deposition system. The simulated results for this work show that the dominant loss mechanism is the low absorption in the a-Si layer thickness. The device results show that even without light trapping, texturing, optimizations, and with minority carrier lifetimes ~ 18 μs, the structure can have realistic voltages ~ 613 mV and efficiencies ~ 12.4%.