Design and implementation of FPGA based wavepipelined fast convolver

A new parallel/serial convolver scheme with wavepipelining is proposed first. The design of the wavepipelined (WP) convolver using FPGAs is considered next. Convolvers with and without wavepipelining are implemented using Xilinx XC4006E FPGAs for convolving two sequences each with 8 bit accuracy and sequence length 8. The convolver without wavepipelining requires 125 CLBs and permits a minimum sampling period of 176 nsec. The WP convolver requires 217 CLBs and permits a minimum sampling period of 92 nsec. Further the multipliers in the WP convolver do not require the latches and an ASIC for a large WP convolver can result in significant savings in area and power. Finally three schemes for increasing the sampling rate of the WP convolver are suggested