Title :
Technology mapping with layout constraints
Author :
Zanden, N.V. ; Wu, C. H Allen ; Gajski, Daniel
Author_Institution :
Dept. of Comput. Sci., Illinois Univ., Urbana, IL, USA
Abstract :
An examination is made of how logic synthesis systems can incorporate layout parameters to better meet designer constraints. The author define an algorithm and present a synthesis tool for technology mapping with custom layout generators. Experimental results indicate that such an approach produces faster and denser layouts and permits greater area/time tradeoffs than traditional logic synthesis systems
Keywords :
circuit layout; logic design; area/time tradeoffs; custom layout generators; denser layouts; designer constraints; layout parameters; logic synthesis systems; synthesis tool; technology mapping; Chip scale packaging; Computer science; Constraint optimization; Design optimization; Libraries; Logic arrays; Logic design; Parasitic capacitance; Productivity; Routing;
Conference_Titel :
VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on
Conference_Location :
Taipei
DOI :
10.1109/VTSA.1989.68619
