A reconfigurable architecture for IP Multimedia Subsystem session setup

The architecture of IP Multimedia Subsystem (IMS) enables converged voice, video, and data services and contains mechanisms related to session and connection control. Numerous protocols are used to perform IMS operations however the Session Initiation Protocol (SIP) plays a central role in the functionality of IMS. With increased demand for multimedia communications functionality, a software implementation of IMS limits performance and increases power consumption when controlling applications through devices like gateways, proxies and application servers. Therefore a strong desire exists to implement SIP using low power consumption hardware platforms very fast time responses. The large integration scale of the present chip technology allows for implementing all SIP mechanisms and interfaces in a single integrated chip or ASIC. In this paper, a reconfigurable hardware implementation of the session setup of IMS is described based on a hardware implementation of SIP.