Title :
A 3-mW, 270-Mbps, Clock-Edge Modulated Serial Link for Mobile Displays
Author :
Choe, Won-Jun ; Lee, Bong-Joon ; Jaeha Kim ; Jeong, Deog-Kyoon ; Gyudong Kim
Author_Institution :
Sch. of Electr. Eng. & Comput. Sci., Seoul Nat. Univ.
Abstract :
In this paper, a single channel clock-edge modulated serial link for mobile display interface is presented. Clock edge modulation (CEM) enables all necessary signals between a graphic processor and a LCD timing controller to be transferred over a single, DC-balanced differential channel, thus greatly saving the power and costs of the existing parallel lines. A simple DLL-based CEM decoder is described that recovers the data with low power consumption and high jitter tolerance. The use of a voltage-mode driver and a single-side termination further reduces the power. A prototype CEM transceiver was implemented in a 0.18mum CMOS process and dissipates 3.12mW when operating at 270-Mb/s and 1.2V
Keywords :
CMOS integrated circuits; delay lock loops; display devices; driver circuits; jitter; transceivers; 0.18 micron; 1.2 V; 270 Mbit/s; 3 mW; 3.12 mW; CEM transceiver; CMOS process; DC-balanced differential channel; DLL-based CEM decoder; LCD timing controller; clock edge modulation; clock-edge modulated serial link; delay lock loop; graphic processor; jitter tolerance; mobile display interface; voltage-mode driver; Clocks; Costs; Decoding; Energy consumption; Graphics; Jitter; Liquid crystal displays; Signal processing; Timing; Voltage;
Conference_Titel :
Asian Solid-State Circuits Conference, 2005
Conference_Location :
Hsinchu
Print_ISBN :
0-7803-9162-4
Electronic_ISBN :
0-7803-9163-2
DOI :
10.1109/ASSCC.2005.251803
