Title :
Hardware compression speeds on bitmap fail display
Author :
Brown, Ben ; Donaldson, John ; Gage, Bob ; Joffe, Alexander
Author_Institution :
Teradyne Inc., Beaverton, OR, USA
Abstract :
A unique lossless data compression algorithm has been implemented into a Bitmap Display Processor. This scanner hardware will allow massive non-lossy compression of bitmap failure images on the order of 10000 to one. The capability should allow new opportunities for testing speed and qualities, with small file sizes and fast image updates
Keywords :
automatic test equipment; automatic testing; data compression; fault diagnosis; integrated circuit testing; integrated memory circuits; random-access storage; signal processing equipment; Bitmap Display Processor; VLSI testing; bitmap fail display; bitmap failure images; compressor timing analysis; data compression algorithm; embedded memory testing; hardware compression speeds; scanner; Data compression; Displays; Encoding; Failure analysis; Hardware; Image coding; Image storage; Random access memory; Read-write memory; Testing;
Conference_Titel :
Test Conference, 1997. Proceedings., International
Conference_Location :
Washington, DC
Print_ISBN :
0-7803-4209-7
DOI :
10.1109/TEST.1997.639598
