RTL dynamic power optimization for FPGAs

As FPGA devices grow in size and speed, power consumption is becoming a limiting problem. In this document, a dynamic power optimization CAD tool for FPGAs that is applied at the register transfer level (RTL) during design synthesis is described. The automatic design transformations implemented by this tool reduce dynamic power by eliminating unnecessary computation by functional units when unit results are not needed. Our new guarded evaluation algorithm locates design functional units that may perform unnecessary computation under specific unit input conditions. Once located, functional unit input logic is modified so that the function will remain dormant when the output of the functional unit is unused. This approach reduces unnecessary signal transitions, thus saving dynamic power. To locate the most desirable functional units for guarded evaluation, an area, depth, and switching activity estimation flow is presented that provides high-level estimates to aid in RTL design transformation. Our approach has been integrated into a design flow for Altera Cyclone II devices. Experiments show that, although not all designs benefit from our approach, an average 12% reduction in dynamic energy can be achieved for a subset of benchmark designs with suitable functional units.