DocumentCode
2736128
Title
A 14-bit 20-MS/s Pipelined ADC with Digital Distortion Calibration
Author
Daito, Mutsuo ; Matsui, Hirofumi ; Ueda, Masaya ; Iizuka, Kunihiko
Author_Institution
Devices Technol. Res. Labs., Sharp Corp., Nara
fYear
2005
fDate
Nov. 2005
Firstpage
61
Lastpage
64
Abstract
We present a 14-bit 20-MS/s pipelined analog-to-digital converter (ADC) using a new digital distortion calibration technique. The calibration parameters are obtained using the same system as the conventional digital gain calibration. The ADC has been fabricated in a 0.18-mum CMOS process and consumes 33.7 mW at 2.8 V. With the calibration it achieves 15-dB improvement of the third-order nonlinearity. The measured SNDR and SFDR are 71.6 dB and 82.3 dB respectively
Keywords
CMOS integrated circuits; analogue-digital conversion; calibration; distortion; 0.18 micron; 14 bit; 2.8 V; 33.7 mW; CMOS process; digital distortion calibration; digital gain calibration; pipelined analog-to-digital converter; Analog-digital conversion; Calibration; Capacitors; Circuits; Energy consumption; Operational amplifiers; Power amplifiers; Sampling methods; Transfer functions; Voltage;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Solid-State Circuits Conference, 2005
Conference_Location
Hsinchu
Print_ISBN
0-7803-9163-2
Electronic_ISBN
0-7803-9163-2
Type
conf
DOI
10.1109/ASSCC.2005.251807
Filename
4017531
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