DocumentCode
2736159
Title
Practical Synthesis of 13-bit 40-MSample/s Pipelined ADC
Author
Chien, Y.T. ; Ma, G.-K. ; Mukherjee, T.
Author_Institution
SoC Technol. Center, Ind. Technol. Res. Inst., Hsinchu
fYear
2005
fDate
Nov. 2005
Firstpage
69
Lastpage
72
Abstract
A 13-bit pipelined ADC achieving 67 dB SNDR without digital calibration while consuming 313mW @ 3.3V 40 MSPS is designed using analog synthesis tools. The MDACs in the pipeline have identical topology and can be synthesized to optimize pipeline performance in less than I day. Figure of merit of the three test keys comparing a manually designed, partially synthesized, and fully synthesized ADC is reported showing the efficacy and efficiency of the proposed approach
Keywords
analogue-digital conversion; pipeline processing; 13 bit; 13-bit pipelined ADC; 3.3 V; 313 mW; SNDR; analog synthesis tools; analog to digital converters; Calibration; Circuit noise; Circuit simulation; Circuit synthesis; Circuit testing; Operational amplifiers; Phase noise; Pipelines; Sampling methods; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
Asian Solid-State Circuits Conference, 2005
Conference_Location
Hsinchu
Print_ISBN
0-7803-9163-2
Electronic_ISBN
0-7803-9163-2
Type
conf
DOI
10.1109/ASSCC.2005.251809
Filename
4017533
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