Title :
A 5.2GHz CMOS fractional-n frequency synthesizer with a MASH delta-sigma modulator
Author :
Chen, Chin-Ying ; Ho, Jyh-Jier ; Liou, Wan-Rone ; Hsiao, Robert Y.
Author_Institution :
Dept. of Comput. Sci. & Inf. Eng., Fortune Inst. of Technol., Kaohsiung
Abstract :
A 5-GHz CMOS fractional-N frequency synthesizer with a delta-sigma modulator is designed in this paper. The frequency dividers are composed of an injection-locked frequency divider and a programmable divider. In consideration of low power consumption, we use an injection-locked frequency divider as the first stage prescaler. The loop filter is a second-order passive filter. The delta-sigma modulator is MASH 1-1-1 architecture. The VCO exhibits a phase noise of-116dBc/Hz at 1MHz offset frequency and an output frequency ranges from 4.91GHz to 5.38GHz. TSMC 0.18-mum CMOS process is used for this frequency synthesizer design and simulation. The frequency resolution of this fractional-N frequency synthesizer is 27 KHz and the locking time is 8 mus.
Keywords :
CMOS analogue integrated circuits; delta-sigma modulation; field effect MMIC; frequency dividers; frequency synthesizers; passive filters; voltage-controlled oscillators; MASH delta-sigma modulator; TSMC CMOS process; VCO; fractional-n frequency synthesizer; frequency 4.91 GHz to 5.38 GHz; injection-locked frequency divider; low power consumption; programmable divider; second-order passive filter; size 0.18 mum; Bandwidth; CMOS technology; Delta modulation; Energy consumption; Frequency conversion; Frequency synthesizers; Multi-stage noise shaping; Phase locked loops; Phase noise; Voltage-controlled oscillators; 0.18-μm CMOS process; MASH 1-1-1 architecture; delta-sigma modulator; frequency synthesizer;
Conference_Titel :
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4244-2166-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2008.4616905
