A hardware-aware process for the design of low-power pulse-shaping filters

A design process for decreasing the average dynamic power consumption of any pulse-shaping filter (PSF) for spread-spectrum communication systems is presented. The process begins with the development of a power consumption approximation function derived from a transistor-level model of the adder used to compute the PSF outputs. This function is then used as the cost function in a simulated annealing search through a set of candidate PSFs produced by perturbing the ideal PSF coefficients. Using a set of PSFs indicative of what would be found in a real application, our process found alternative PSFs with estimated average dynamic power consumption savings ranging from 23.3% to 74.5%. The effects of our process on the frequency response of the PSF, discussed and quantified in this work, are minimal.