RESORT: a gate-level rule-based expert system optimization with resizing and testability enhancement

Author

Wang, J.S. ; Lai, Feipei

Author_Institution

Dept. of Inf. Eng., Tatung Inst. of Technol., Taipei, Taiwan

fYear

1989

fDate

17-19 May 1989

Firstpage

237

Lastpage

241

Abstract

A rule-based expert system for CMOS (complementary-metal-oxide semiconductor) combinational logic optimization is presented. The system, called RESORT (Rule-based Expert System Optimization with Resizing and Testability enhancement), accepts a gate-level description of a combinational logic circuit as input and generates a functionally equivalent one with delay and area within specified constraints. The actions of RESORT are similar to those performed by logic designers in transistor resizing and logic pattern replacement during manual optimizations. Testability enhancement (redundancy elimination) is also provided by RESORT. Because the optimizing rules in the rule base come from the expertise of the logic designers, the resulting circuit is not only close to the optimal outcome but also practical

Keywords

CMOS integrated circuits; combinatorial circuits; expert systems; integrated logic circuits; logic CAD; CMOS; RESORT; area; combinational logic optimization; delay; functionally equivalent; gate-level description; gate-level rule-based expert system optimization; redundancy elimination; resizing; testability; testability enhancement; CMOS logic circuits; Circuit testing; Combinational circuits; Constraint optimization; Delay; Design optimization; Expert systems; Logic design; Logic testing; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Technology, Systems and Applications, 1989. Proceedings of Technical Papers. 1989 International Symposium on

Conference_Location

Taipei

Type

conf

DOI

10.1109/VTSA.1989.68621

Filename

68621