A technique for low power dynamic circuit design in 32nm double-gate FinFET technology

In this paper, a new technique is presented for low power high-speed dynamic circuits design using double gate FinFET. In this technique, the clock signal is used to control the threshold voltage of the front gate; the threshold voltage of the front gate is reduced during the evaluation phase for a fast transition and increased during the pre-charge or standby phase to reduce the leakage current (this is accomplished by connecting the back gate to the clock signal of the dynamic circuit). By controlling the threshold voltage of the FinFET, the proposed technique achieves a power reduction of up to 34%, and no delay compared to other approaches at a 32 nm feature size.