Title :
A technique for low power dynamic circuit design in 32nm double-gate FinFET technology
Author :
Kim, Young Bok ; Kim, Yong-Bin ; Lombardi, Fabrizio
Author_Institution :
Dept. of Electr. & Comput. Eng., Northeastern Univ., Boston, MA
Abstract :
In this paper, a new technique is presented for low power high-speed dynamic circuits design using double gate FinFET. In this technique, the clock signal is used to control the threshold voltage of the front gate; the threshold voltage of the front gate is reduced during the evaluation phase for a fast transition and increased during the pre-charge or standby phase to reduce the leakage current (this is accomplished by connecting the back gate to the clock signal of the dynamic circuit). By controlling the threshold voltage of the FinFET, the proposed technique achieves a power reduction of up to 34%, and no delay compared to other approaches at a 32 nm feature size.
Keywords :
MOSFET circuits; integrated circuit design; low-power electronics; network synthesis; power consumption; clock signal; double-gate FinFET technology; feature size; high-speed dynamic circuits design; low power dynamic circuit design; power reduction; size 32 nm; CMOS technology; Circuit synthesis; Clocks; Design engineering; Energy consumption; FinFETs; Power engineering and energy; Power engineering computing; Threshold voltage; Voltage control;
Conference_Titel :
Circuits and Systems, 2008. MWSCAS 2008. 51st Midwest Symposium on
Conference_Location :
Knoxville, TN
Print_ISBN :
978-1-4244-2166-4
Electronic_ISBN :
1548-3746
DOI :
10.1109/MWSCAS.2008.4616915