Title :
Optimal evaluation clocking of self-resetting domino pipelines
Author :
Yun, Kenneth Y. ; Dooply, Ayoob E.
Author_Institution :
Dept. of Electr. & Comput. Eng., California Univ., San Diego, La Jolla, CA, USA
Abstract :
We describe a high performance clocking methodology for domino pipelines. Our technique maximizes the clock rate of the circular pipeline (“ring”) while maintaining the ring cycle time to be the worst-case combinational logic delay around the ring. It is relatively immune to global clock skew, incurs no latch overhead, allows up to 50% time borrowing, and offers a robust way of preventing race-through problems, adjusted for the worst-case time borrowing
Keywords :
circuit CAD; circuit optimisation; clocks; combinational circuits; delays; logic CAD; pipeline processing; circular pipeline; clock rate; high performance clocking methodology; optimal evaluation clocking; race-through problems; ring cycle time; self-resetting domino pipelines; worst-case combinational logic delay; worst-case time borrowing; Circuits; Clocks; Delay effects; Drives; Explosives; Latches; Logic; Pipelines; Robustness; Timing;
Conference_Titel :
Design Automation Conference, 1999. Proceedings of the ASP-DAC '99. Asia and South Pacific
Conference_Location :
Wanchai
Print_ISBN :
0-7803-5012-X
DOI :
10.1109/ASPDAC.1999.759728
